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1 data sheet no. pd60238 reve irs2153(1)d(s)pbf self-oscillating half-bridge driver ic features product summary v offset 600 v max duty cycle 50% driver source/sink current 180 ma/260 ma typ. v clamp 15.4 v typ. ? integrated 600 v half- bridge gate driver ? ? c t , r t programmable oscillator ? 15.4 v zener clamp on v cc ? micropower startup ? non-latched shutdown on c t pin (1/6th v cc ) ? internal bootstrap fet ? excellent latch immunity on all inputs and outputs ? +/- 50 v/ns dv/dt immunity ? esd protection on all pins ? 8-lead soic or pdip package ? internal deadtime deadtime 1.1 s typ. (irs2153d) 0.6 s typ. (irs21531d) description the irs2153(1)d is based on the popular ir2153 self- oscillating half-bridge gate driver ic using a more advanced silicon platform, and incorporates a high voltage half-bridge gate driver with a front end oscillator similar to the industry standard cmos 555 timer. hvic and latch immune cmos technologies enable rugged monolithic construction. the out put driver features a high pulse current buffer stage designed for minimum driver cross-conduction. noise immunity is achieved with low di/dt peak of the gate drivers. package pdip8 so8 irs2153(1)dpbf irs2153(1)dspbf typical connection diagram rtct com vcc 1 2 3 4 7 6 5 8 irs2153(1)d lo vs ho vb cboot mhs mls l rl rvcc rt ct cvcc + ac rectified line - ac rectified line downloaded from: http:///
2 irs2153(1)d absolute maximum ratings absolute maximum ratings indicate sustained limit s beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ra tings are measured under board mounted and still air conditions. parameter symbol definition min. max. units v b high side floating supply voltage -0.3 625 v s high side floating supply offset voltage v b - 25 v b + 0.3 v ho high side floating output voltage v s C 0.3 v b + 0.3 v lo low side output voltage -0.3 v cc + 0.3 v i rt r t pin current -5 5 ma v rt r t pin voltage -0.3 v cc + 0.3 v ct c t pin voltage -0.3 v cc + 0.3 v i cc supply current (note 1) --- 20 i omax maximum allowable current at lo and ho due to external power transistor miller effect. -500 500 ma dv s /dt allowable offset voltage slew rate -50 50 v/ns p d maximum power dissipation @ t a +25 oc, 8-pin dip --- 1.0 p d maximum power dissipation @ t a +25 oc, 8-pin soic --- 0.625 w r thja thermal resistance, junction to ambient, 8-pin dip --- 85 r thja thermal resistance, junction to ambient, 8-pin soic --- 128 oc/w t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 oc note 1: this ic contains a zener clamp structure between the chip v cc and com which has a nominal breakdown voltage of 15.4 v. please note that this supply pin should not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section. downloaded from: http:///
3 irs2153(1)d recommended operating conditions for proper operation the device should be used within the recommended conditions. parameter symbol definition min. max. units v bs high side floating supply voltage v cc - 0.7 v clamp v s steady state side floating supply o ffset voltage -3.0 (note 2) 600 v cc supply voltage v ccuv + +0.1 v v cc clamp v i cc supply current (note 3) 5 ma t j junction temperature -40 125 oc note 2: it is recommended to avoid output switching condi tions where the negative-going spikes at the v s node would decrease v s below ground by more than -5 v. note 3: enough current should be supplied to the v cc pin of the ic to keep the internal 15.6 v zener diode clamping the voltage at this pin. recommended component values parameter symbol component min. max. units r t timing resistor value 1 --- k ? c t c t pin capacitor value 330 --- pf v bias (v cc , v bs ) = 14 v, v s =0 v and t a = 25 c, clo = cho = 1 nf. frequency vs. rt 10 100 1,000 10,000 100,000 1,000,000 1,000 10,000 100,000 1,000,000 rt (ohm) frequency (hz) 330pf 470pf 1nf 2.2nf 4.7nf 10nf ct values for further information, see fig. 12. downloaded from: http:///
4 irs2153(1)d electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf, v s =0 v and t a = 25 c unless otherwise specified. the output voltage and current (v o and i o ) parameters are referenced to com and are applicable to the respecti ve output leads: ho or lo. clo = cho = 1 nf. symbol definition min typ max units test conditions low volt a ge su pply ch a r a ct e r ist ics v ccuv + rising v cc undervoltage lockout threshold 10.0 11.0 12.0 v ccuv - falling v cc undervoltage lockout threshold 8.0 9.0 10.0 v ccuvhys v cc undervoltage lockout hysteresis 1.6 2.0 2.4 v i qccuv micropower startup v cc supply current --- 130 170 v cc v ccuv- i qcc quiescent v cc supply current --- 800 1000 a i cc v cc supply current --- 1.8 --- ma r t = 36.9 k ? v cc clamp v cc zener clamp voltage 14.4 15.4 16.8 v i cc = 5 ma floa t in g su pply ch a r a ct e r ist ics i qbs quiescent v bs supply current --- 60 80 a v bsuv+ v bs supply undervoltage positive going threshold 8.0 9.0 9.5 v bsuv- v bs supply undervoltage negative going threshold 7.0 8.0 9.0 v i lk offset supply leakage current --- --- 50 a v b = v s = 600 v oscilla t or i / o ch a r a ct e r ist ics 18.4 19.0 19.6 r t = 36.5 k ? f osc oscillator frequency 88 93 100 khz r t = 7.15 k ? d r t pin duty cycle --- 50 --- % f o < 100 khz i ct c t pin current --- 0.02 1.0 a i ctuv uv-mode c t pin pulldown current 0.20 0.30 0.6 ma v cc = 7 v v ct+ upper c t ramp voltage threshold --- 9.32 --- v ct- lower c t ramp voltage threshold --- 4.66 --- v ctsd c t voltage shutdown threshold 2.2 2.3 2.4 v --- 10 50 i rt = -100 a v rt+ high-level r t output voltage, v cc - v rt --- 100 300 i rt = -1 ma --- 10 50 i rt = 100 a v rt- low-level r t output voltage --- 100 300 i rt = 1 ma v rtuv uv-mode r t output voltage --- 0 100 v cc v ccuv- --- 10 50 i rt = -100 a, v ct = 0 v v rtsd sd-mode r t output voltage, v cc - v rt --- 100 300 mv i rt = -1 ma, v ct = 0 v downloaded from: http:///
5 irs2153(1)d electrical characteristics v bias (v cc , v bs ) = 14 v, c t = 1 nf, v s =0 v and t a = 25 c unless otherwise specified. the output voltage and current (v o and i o ) parameters are referenced to com and are applicable to the respective output leads: ho or lo. clo = cho = 1 nf. symbol definition min typ max units test conditions ga t e d r ive r ou t pu t ch a r a ct e r ist ics v oh high-level output voltage --- v cc --- v ol low-level output voltage --- com --- i o = 0 a v ol_uv uv-mode output voltage --- com --- v i o = 0 a , v cc v ccuv- t r output rise time --- 120 220 t f output fall time --- 50 80 t sd shutdown propagation delay --- 350 --- ns t d output deadtime (ho or lo ) (irs2153d) 0.65 1.1 1.75 s t d output deadtime (ho or lo ) (irs21531d) 0.35 0.6 0.85 s i o+ output source current --- 180 --- i o- output sink current --- 260 --- ma boot st r a p fet ch a r a ct e r ist ics v b_on v b when the bootstrap fet is on --- 13.7 --- v i b_cap v b source current when fet is on 40 55 --- c bs =0.1 uf i b_10v v b source current when fet is on 10 12 --- ma v b =10 v downloaded from: http:///
6 irs2153(1)d lead definitions rtct com vcc 1 2 3 4 7 6 5 8 irs2153(1)d lo vs ho vb lead symbol description v cc logic and internal gate drive supply voltage r t oscillator timing resistor input c t oscillator timing capacitor input com ic power and signal ground lo low-side gate driver output v s high voltage floating supply return ho high-side gate driver output v b high side gate driver floating supply downloaded from: http:///
7 irs2153(1)d functional block diagram vb pulse gen delay hv level shift pulse filter lo vs rs q ct rt rq s q ho - - - + + + rr r/2 r/2 uv detect dead time dead time r1 s q r2 2 3 5 6 7 8 com 4 vcc 15.4v 1 bootstrap drive m1 downloaded from: http:///
8 irs2153(1)d timing diagram operating mode dt dt vrt vcc 1/3 vcc 2/3 vcc vct irt vcc vccuv+ lo vcc ho vcc 1/6 vcc switching time waveform deadtime waveform tr tf 90% 10% ho lo dtlo lo ho 10% 10% 90% 90% dtho fault mode: ct <1/6*vcc downloaded from: http:///
9 irs2153(1)d functional description under-voltage lock-out mode (uvlo) the under-voltage lockout mode (uvl o) is defined as the state the ic is in when v cc is below the turn-on threshold of the ic. the irs2153(1)d under voltage lock-out is designed to maintain an ultra low supply current of less than 170 a, and to guarantee the ic is fully functional before t he high and low side output drivers are activated. during under voltage lock-out mode, the high and low-side driver outputs ho and lo are both low. supply voltage rtct com vcc 1 2 3 4 7 6 5 8 irs2153(1)d lo vs ho vb cboot mhs mls l rl rvcc rt ct cvcc + ac rectified line - ac rectified line fig. 1 typical connection diagram fig. 1 shows an example of suppl y voltage. the start-up capacitor (c vcc ) is charged by current through supply resistor (r vcc ) minus the start-up current drawn by the ic. this resistor is chosen to provide sufficient current to s upply the irs2153(1)d from the dc bus. c vcc should be large enough to hold the voltage at vcc above the uvlo threshold for one hal f cycle of the line voltage as it will only be charged at the peak, typically 0.1 uf. it will be necessary for r vcc to dissipate around 1 w. the use of a two diode charge pump made of dc1, dc2 and cvs (fig. 2) from the half bridge (v s ) is also possible however the above approach is simplest and the dissipation in r vcc should not be unacceptably high. rtct com vcc 1 2 3 4 7 6 5 8 irs2153(1)d lo vs ho vb cboot mhs mls l rl rvcc rt ct cvcc + ac rectified line - ac rectified line dc1 dc2 cvs fig. 2 charge pump circuit the supply resistor (r vcc ) must be selected such that enough supply current is available over all operating conditions. once the capacitor voltage on v cc reaches the start-up threshold v ccuv+ , the ic turns on and ho and lo begin to oscillate. bootstrap mosfet the internal bootstrap fe t and supply capacitor (c boot ) comprise the supply voltage for the high side dr iver circuitry. the internal boostrap fet only turns on when lo is high. to guarantee that the high-side supply is charged up before the first pulse on pin ho, the first pulse from the output drivers comes from the lo pin. normal operating mode once the v ccuv+ threshold is passed, the mosfet m1 opens, rt increases to approximately v cc (v cc -v rt+) and the external ct capacitor starts charging. on ce the ct voltage reaches v ct - (about 1/3 of v cc ), established by an internal resistor ladder, lo turns on with a delay equivalent to the deadtime (t d ). once the ct voltage reaches v ct+ (approximately 2/3 of v cc ), lo goes low, rt goes down to approximately ground (v rt- ), the ct capacitor discharges and the deadtime circuit is activated. at the end of the deadtime, ho goes high. once the ct voltage reaches v ct-, ho goes low, rt goes high again, the deadtime is activated. at the end of the deadtime, lo goes hi gh and the cycle starts over again. the following equation provides the oscillator frequency: ct rt f 453 .1 1 ~ this equation can vary slightly from actual measurements due to internal comparator over- and under-shoot delays. for a more accurate determination of t he output frequency, the frequency characteristic curves should be used (rt vs. frequency, page 3). shut-down if ct is pulled down below v ctsd (approximately 1/6 of v cc ) by an external circuit, ct doesn t charge up and oscillation stops. lo is held low and the bootstrap fet is off. oscillation will resume once ct is able to charge up again to v ct- . downloaded from: http:///
10 irs2153(1)d 18 18.2 18.4 18.6 18.8 19 11 12 13 14 15 16 vcc(v) frequency (khz ) freq vs vcc 90 92 94 96 98 100 -25 0 25 50 75 100 125 temperature(c) frequency (khz ) freq vs temp fig. 3 fig. 4 0.9 1 1.1 1.2 1.3 1.4 11 12 13 14 15 16 v cc( v ) dt(us) dt vs vcc 0.75 0.85 0.95 1.05 1.15 1.25 -25 0 25 50 75 100 125 temperature(c) dt(us) dt vs temp fig. 5 (irs2153d) fig. 6 (irs2153d) tj vs. frequency (soic) 0 10 20 30 40 50 60 70 80 90 20 70 120 frequency(khz) temperature(c) 15 16 17 -25 0 25 50 75 100 125 temperature (c) vcc (v) vcc clamp vs temp fig. 7 fig. 8 downloaded from: http:///
11 irs2153(1)d 0 50 100 150 200 250 300 -25 0 25 50 75 100 125 temperature(c) hocurrent (ma ) isourceho,isinkho vs temp isourceho isinkho 0 50 100 150 200 250 300 -25 0 25 50 75 100 125 temperature(c) lo current (ma) isourcelo,isinklo vs temp isourcelo i s i n k l o fig. 9 fig. 10 0 10 20 30 40 50 60 70 80 -25 0 25 50 75 100 125 temperature(c) ib_cap, ibs_10v (ma) ibcap, ibs10v vs temp ib_ca p ibs_10v voh_ho vs. frequency 0 2 4 6 8 10 12 14 16 0 50 100 150 200 250 300 350 400 frequency (khz) voh_ho (v) with external bs diode no external bs diode t=25c, vs=0v, cho = 1nf fig. 11 fig. 12 voh_ho vs. frequency vs. temp vcc=14v, cho=1nf, vs=0v 0 2 4 6 8 10 12 14 1.46khz 20 k 50 k 75 k 10 0k 12 5k 15 0k 2 0 0k frequency (khz) voh_ho( v) t=-25c t=25c t=75c t=125c fig. 13 downloaded from: http:///
12 irs2153(1)d irs2153(1)dpbf irs2153(1)dspbf downloaded from: http:///
13 irs2153(1)d carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c downloaded from: http:///
14 irs2153(1)d part marking information order information 8-lead pdip irs2153dpbf 8-lead pdip IRS21531DPBF 8-lead soic irs2153dspbf 8-lead soic irs21531dspbf 8-lead soic tape & reel irs2153dstrpbf 8-lead soic tape & reel irs21531dstrpbf the soic-8 is msl2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 data and specifications subject to change without notice. 6/27/2006 downloaded from: http:///

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